This question was previously asked in

PTCUL AE E&M 2017 Official Paper (Set B)

- 8
- 10
- 9
- 6

Option 3 : 9

**The Sum output bit of a full adder is given by:**

Looking at the Full-Adder circuit, we can see that,

S = A ⊕ B ⊕ C

From full adder circuit,

C_{out} = AB + C_{in} (A ⊕ B)

Now, logic gate for above boolean expression can be drawn as,

Connecting them to a NAND gate, we now have the Full-Adder NAND Equivalent.

**Hence, 9 minimum number of NAND gates requires to implement A ⊕ B ⊕ C or Full-Adder circuit.**

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